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August 2026, HDL Works announces the release and immediate availability of IO
Checker 5.3,
the FPGA and PCB IO verification tool.
IO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins. IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pin device in half an hour.
The Pin view has been extended with 2 icon columns denoting the pin type derived from the FPGA pin file and the alternate device pin type (when set). This makes it easier to see if a pin changed behaviour after pin mapping or if the alternate device pin has a different functionality. The pin icons shown in the pin view and in the device view have been synchronized.
Both Pin- and Signal view toolbars have been extended with a menu and status button. When errors are present a red cross is shown in the status button. The menu button lists functionality available from the main menu bar to simplify access to actions available for the specific view.
The Signal view has been extended with an error column to either show a red/orange error/warning dot. A tooltip in that column shows the related warning or error message(s). Incorrect pin numbers or IO standards are drawn in the error color (red by default).
Added a functional name filter to the button bar. When active, only pins whose label contains the filter text are shown.
When a selection is present draw the not selected pins opaque. This makes it easier to see where the selected pins are located.
Drag & drop:
The ESC key now deselects all pins in the view.
The verification choices have been simplified and the verification wizard has been removed. The default verification mode is changed to automatic, meaning that IO Checker will select the most appropriate verification mode based on the available data.
The severity of the IO Checker verification messages can now be set in the project properties dialog.
Verification has been improved for pins which are a dedicated LVDS pair.
Two new checks are added:
Improvements in the Symbol tool:
Improvements in the wiring tool:
IO Checker 5.3 is available now. Prices begin at € 850 or US$ 1000.
IO Checker can be downloaded and evaluated from the HDL Works website.
HDL Works develops and markets high-performance, intuitive tools for complex HDL design across a wide spectrum of applications. HDL Works currently holds BoardTrace, EASE, HDL Companion and IO Checker in its product portfolio. Headquartered in Ede, The Netherlands, HDL Works is privately held.
HDL Works BV
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BoardTrace, EASE, HDL Companion, IO Checker and Scriptum are trademarks of HDL
Works.
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